View ADP5042_5057736.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Micro PMU with 0.8 A Buck, Two 300 mA LDOs Supervisory, Watchdog and Manual Reset
ADP5042
FEATURES
Input voltage range: 2.3 V to 5.5 V One 0.8 A buck regulator Two 300 mA LDOs 20-lead, 4 mm x 4 mm LFCSP package Initial regulator accuracy: 1% Overcurrent and thermal protection Soft start Undervoltage lockout Open drain processor reset with threshold monitoring 1.5% threshold accuracy over the full temperate range Guaranteed reset output valid to VCC = 1 V Dual watchdog for secure systems Watchdog 1 controls reset Watchdog 2 controls reset and regulators power cycle Buck key specifications Current mode topology for excellent transient response 3 MHz operating frequency Uses tiny multilayer inductors and capacitors Mode pin selects forced PWM or auto PFM/PSM modes 100% duty cycle low dropout mode LDOs key specifications Low VIN from 1.7 V to 5.5 V Stable with1 F ceramic output capacitors High PSRR, 60 dB PSRR up to 1 kHz/10 kHz Low output noise 110 V rms typical output noise at VOUT = 2.8 V Low dropout voltage: 150 mV at 300 mA load -40C to +125C junction temperature range
HIGH LEVEL BLOCK DIAGRAM
RFILT = 30 AVIN VIN1 = 2.3V TO 5.5V VIN1 C5 4.7F OFF VIN2 = 1.7V TO 5.5V ON EN1 VIN2 C1 1F OFF ON EN2 LDO1 (DIGITAL) EN_LDO1 WSTAT BUCK EN_BK MODE VOUT2 AVIN SW VOUT1 PGND FPWM PSM/PWM VOUT2 AT 300mA L1 1H VOUT1 AT 800mA C6 10F
SUPERVISOR
AVIN
nRSTO WDI1 WDI2
MR ON OFF VIN3 = 1.7V TO 5.5V EN3 VIN3 C3 1F
EN_LDO2 LDO2 (ANALOG)
VOUT3 C4 1F
MICROPROCESSOR
C2 1F
VOUT3 AT 300mA
AGND
Figure 1.
GENERAL DESCRIPTION
The ADP5042 combines one high performance buck regulator and two low dropout regulators (LDO) in a small 20-lead LFCSP to meet demanding performance and board space requirements. The high switching frequency of the buck regulator enables use of tiny multilayer external components and minimizes the board space. The MODE pin selects the buck mode of operation. When set to logic high, the buck regulators operate in forced PWM mode. When the MODE pin is set to logic low, the buck regulators operate in PWM mode when the load is around the nominal value. When the load current falls below a predefined threshold the regulator operates in power save mode (PSM) improving the light-load efficiency. The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5042 LDOs extend the battery life of portable devices. The two LDOs maintain power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage. Each regulator is activated by a high level on the respective enable pin. The ADP5042 is available with factory programmable default output voltages and can be set to a wide range of options. The ADP5042 contains supervisory circuits that monitor power supply voltage levels and code execution integrity in microprocessor-based systems. They also provide power-on reset signals. An on-chip dual watchdog timer can reset the microprocessor or power cycle the system (Watchdog 2) if it fails to strobe within a preset timeout period.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2010 Analog Devices, Inc. All rights reserved.
08811-001
ADP5042 TABLE OF CONTENTS
Features .............................................................................................. 1 High Level Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 General Specification ................................................................... 3 Supervisory Specification ............................................................ 3 Buck Specifications....................................................................... 5 LDO1, LDO2 Specifications ....................................................... 5 Input and Output Capacitor, Recommended Specifications .. 6 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Theory of Operation ...................................................................... 18 Power Management Unit ........................................................... 18 Buck Section................................................................................ 19 LDO Section ............................................................................... 20 Supervisory Section ................................................................... 20 Applications Information .............................................................. 23 Buck External Component Selection....................................... 23 LDO Capacitor Selection .......................................................... 24 Supervisory Section ................................................................... 25 PCB Layout Guidelines.............................................................. 26 Evaluation Board Schematics and Artwork ............................ 27 Suggested Layout ........................................................................ 27 Bill of Materials ........................................................................... 28 Application Diagram ................................................................. 28 Factory Programmable Options ................................................... 29 Outline Dimensions ....................................................................... 30 Ordering Guide .......................................................................... 30
REVISION HISTORY
12/10--Revision 0: Initial Version
Rev. 0 | Page 2 of 32
ADP5042 SPECIFICATIONS
GENERAL SPECIFICATION
AVIN, VIN1 = (VOUT1+ 0.5 V) or 2.3 V, whichever is greater, AVIN, VIN1 VIN2, VIN3, TA = 25C, unless otherwise noted. Regulators are enabled. Table 1.
Parameter AVIN UNDERVOLTAGE LOCKOUT Input Voltage Rising Input Voltage Falling SHUTDOWN CURRENT Thermal Shutdown Threshold Thermal Shutdown Hysteresis ENx, WDIx, MODE, WMOD, MR INPUTS Input Logic High Input Logic Low Input Leakage Current (WMOD Excluded) WMOD Input Leakage Current OPEN-DRAIN OUTPUTS nRSTO, WSTAT Output Voltage Open-Drain Reset Output Leakage Current Symbol UVLOAVIN UVLOAVINRISE UVLOAVINFALL IGND-SD TSSD TSSD-HYS VIH VIL VI-LEAKAGE Description TJ = -40C to +125C Min Typ Max 2.25 1.95 ENx = GND ENx = GND, TJ = -40C to +125C TJ rising 0.1 2 150 20 1.2 0.4 0.05 1 50 30 1 Unit V V A A C C V V A A A mV A
2.5 V AVIN 5.5 V 2.5 V AVIN 5.5 V ENx = AVIN or GND ENx = AVIN or GND, TJ = -40C to +125C VWMOD = 3.6 V, TJ = -40C to +125C AVIN = 2.3 V to 5.5 V, InRSTO/WSTAT = 3 mA
VI-LKG-WMOD VOL
SUPERVISORY SPECIFICATION
AVIN, VIN1 = full operating range, TJ = -40C to +125C, unless otherwise noted. Table 2.
Parameter SUPPLY Supply Current (Supervisory Circuit Only) RESET THRESHOLD ACCURACY Min Typ 45 43 VTH VTH 125 Max 55 52 VTH + 0.8% VTH + 1.5% 400 Unit A A V V s Test Conditions/Comments AVIN = 5.5 V, EN1 = EN2 = EN3 = VIN AVIN = 3.6 V, EN1 = EN2 = EN3 = VIN TA = 25C, sensed on VOUTx TJ = -40C to +125C, sensed on VOUTx VTH = VUOT - 50 mV
VTH - 0.8% VTH - 1.5% 50
RESET THRESHOLD TO OUTPUT DELAY GLITCH IMMUNITY (tUOD) RESET TIMEOUT PERIOD WATCHDOG1 (tRP1) Option A Option B RESET TIMEOUT PERIOD WATCHDOG2 (tRP2) VCC TO RESET DELAY (tRD) REGULATORS SEQUENCING DELAY (tD1, tD2) WATCHDOG INPUTS Watchdog 1 Timeout Period (tWD1) Option A Option B
24 160 3.5
30 200 5 150 2
36 240 7
ms ms ms s ms
VIN1 falling at 1 mV/s
81.6 1.28
102 1.6
122.4 1.92
ms sec
Rev. 0 | Page 3 of 32
ADP5042
Parameter Watchdog 2 Timeout Period (tWD2) Option A Option B Option C Option D Option E Option F Option G Option H Watchdog 2 Power Off Period (tPOFF) Option A Option B WDI1 Pulse Width WDI2 Pulse Width Watchdog Status Timeout Period (tWDCLEAR) WDI1 Input Current (Source) WDI1 Input Current (Sink) WDI2 Internal Pull-Down MANUAL RESET INPUT MR Input Pulse Width MR Glitch Rejection MR Pull-Up Resistance MR to Reset Delay Min 6 3.2 6.4 11.2 25.6 51.2 102.4 Typ Max Unit sec min min min min min min ms ms ns s sec A A k s ns k ns Test Conditions/Comments 7.5 9 Watchdog 2 disabled 4 4.8 8 9.6 16 19.2 32 38.4 64 76.8 128 153.8 210 400 80 8 8 -30 11.2 15 -25 45 20 -14
VIL = 0.4 V, VIH = 1.2 V VIL = 0.4 V, VIH = 1.2 V VWDI1 = VCC, time average VWDI1 = 0, time average
1 25 220 52 280 80
VCC = 5 V
Rev. 0 | Page 4 of 32
ADP5042
BUCK SPECIFICATIONS
AVIN, VIN1 = 3.6 V, VOUT1 = 1.8 V, TJ= -40C to +125C for minimum/maximum specifications, L = 1 H, COUT = 10 F, and TA = 25C for typical specifications, unless otherwise noted. 1 Table 3.
Parameter INPUT CHARACTERISTICS Input Voltage Range (VIN1) OUTPUT CHARACTERISTICS Output Voltage Accuracy Test Conditions/Comments Min 2.3 PWM mode, TA= 25 C , ILOAD = 100 mA PWM mode VIN1 = 2.3 V to 5.5 V, PWM mode, ILOAD = 1 to 800 mA -1 -2 -3 100 ILOAD = 0 mA, device not switching ENx = 0 V, TA = TJ = -40C to +125C PFET PFET, AVIN = VIN1 = 5 V NFET NFET, AVIN = VIN1 = 5 V PFET switch peak current limit EN1 = 0 V 21 0.2 180 140 170 150 1360 75 3.0 250 35 1.0 240 190 235 210 1600 3.5 Typ Max 5.5 +1 +2 +3 Unit V % % % mA A A m m m m mA MHz s
PWM TO POWER SAVE MODE CURRENT THRESHOLD INPUT CURRENT CHARACTERISTICS DC Operating Current Shutdown Current SW CHARACTERISTICS SW On Resistance
Current Limit ACTIVE PULL-DOWN OSCILLATOR FREQUENCY START-UP TIME
1
1100 2.5
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
LDO1, LDO2 SPECIFICATIONS
AVIN = 3.6 V, VIN2, VIN3 = (VOUT3 + 0.2 V) or 2.3 V, whichever is greater; AVIN, VIN1 VIN2, VIN3; IOUT = 10 mA; CIN = COUT = 1 F; TA = 25C, unless otherwise noted. Table 4.
Parameter INPUT VOLTAGE RANGE OPERATING SUPPLY CURRENT (per LDO) Symbol VIN2, VIN3 IGND Conditions TJ = -40C to +125C IOUT = 0 A, VOUT = 3.3 V IOUT = 0 A, VOUT = 3.3 V, TJ = -40C to +125C IOUT = 10 mA IOUT = 10 mA, TJ = -40C to +125C IOUT = 200 mA IOUT = 200 mA, TJ = -40C to +125C IOUT = 10 mA 100 A < IOUT < 300 mA VIN2, VIN3 = (VOUT2, VOUT3 + 0.5 V) to 5.5 V 100 A < IOUT < 300 mA VIN2, VIN3 = (VOUT2, VOUT3 + 0.5 V) to 5.5 V TJ = -40C to +125C VIN2, VIN3 = (VOUT2, VOUT3 + 0.5 V) to 5.5 V IOUT3 = 1 mA TJ = -40C to +125C
Rev. 0 | Page 5 of 32
Min 1.7
Typ 15
Max 5.5
Unit V A A A A A A % % %
50 67 105 100 -1 -2 -3 245 +1 +2 +3
FIXED OUTPUT VOLTAGE ACCURACY
VOUT2, VOUT3
REGULATION Line Regulation
VOUT2/VIN2 VOUT3/VIN3
-0.03
+0.03
%/ V
ADP5042
Parameter Load Regulation1 Symbol VOUT2/IOUT2 VOUT3/IOUT3 Conditions IOUT2, VOUT3 = 1 mA to 200 mA IOUT2, VOUT3 = 1 mA to 200 mA TJ = -40C to +125C VOUT2, VOUT3 = 3.3 V IOUT2, IOUT3 = 10 mA IOUT2, IOUT3 = 10 mA, TJ = -40C to +125C IOUT2, IOUT3 = 200 mA IOUT2, IOUT3 = 200 mA, TJ = -40C to +125C EN2/EN3 = 0 V VOUT2, VOUT3 = 3.3 V TJ = -40C to +125C 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 3.3 V 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 2.8 V 10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 1.5 V 10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 3.3 V 10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 2.8 V 10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 1.5 V 1 kHz, VIN2, VIN3 = 3.3 V, VOUT2, OUT3 = 2.8 V, IOUT = 100 mA 100 kHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V, IOUT = 100 mA 1 MHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V, IOUT = 100 mA Min Typ 0.002 Max Unit %/mA %/mA
0.0075
DROPOUT VOLTAGE2
VDROPOUT
4 5 60 100 600 85 470 123 110 59 140 129 66 66 57 60
ACTIVE PULL-DOWN START-UP TIME CURRENT-LIMIT THRESHOLD3 OUTPUT NOISE
RPDLDO TSTART-UP ILIMIT OUTLDO2NOISE
335
OUTLDO1NOISE
mV mV mV mV s mA V rms V rms V rms V rms V rms V rms dB dB dB
POWER SUPPLY REJECTION RATIO
PSRR
1 2
Based on an end-point calculation using 1 mA and 100 mA loads. Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above 2.3 V. 3 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
Table 5.
Parameter MINIMUM OUTPUT CAPACITANCE (BUCK)1 MINIMUM INPUT AND OUTPUT CAPACITANCE2 (LDO1, LDO2) CAPACITOR ESR
1
Symbol CMIN1 CMIN23 RESR
Conditions TJ = -40C to +125C TJ = -40C to +125C TJ = -40C to +125C
Min 7 0.70 0.001
Typ
Max 40 1
Unit F F
The minimum output capacitance should be greater than 4.7 F over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. 2 The minimum input and output capacitance should be greater than 0.70 F over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended, Y5V and Z5U capacitors are not recommended for use with LDOs or the buck.
Rev. 0 | Page 6 of 32
ADP5042 ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter AVIN, VINx, VOUTx, ENx, MODE, MR, WDIx, WMOD, WSTAT, nRSTO to GND Storage Temperature Range Operating Junction Temperature Range Soldering Conditions ESD Human Body Model ESD Charged Device Model ESD Machine Model Rating -0.3 V to +6 V -65C to +150C -40C to +125C JEDEC J-STD-020 3000 V 1500 V 100 V
Junction-to-ambient thermal resistance (JA) of the package is based on modeling and calculation using a 4-layer board. The junction-to-ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of JA may vary, depending on PCB material, layout, and environmental conditions. The specified value of JA is based on a four-layer, 4" x 3", 2.5 oz copper board, as per JEDEC standard. For additional information, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale (LFCSP).
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 7. Thermal Resistance
Package Type 20-Lead, 0.5 mm pitch LFCSP JA 38 JC 4.2 Unit C/W
THERMAL DATA
Absolute maximum ratings apply individually only, not in combination. The ADP5042 can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that the junction temperature is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated. In applications with moderate power dissipation and low PCB thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature of the device is dependent on the ambient temperature, the power dissipation of the device (PD), and the junction-to-ambient thermal resistance of the package. Maximum junction temperature is calculated from the ambient temperature and power dissipation using the formula TJ = TA + (PD x JA)
ESD CAUTION
Rev. 0 | Page 7 of 32
ADP5042 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
20 19 18 17 16
15 14 13 12 11
MR WDI1 WMOD MODE EN2
NC VOUT3 VIN3 EN3 nRSTO
1 2 3 4 5
AD5042
TOP VIEW
WSTAT VOUT2 VIN2 WDI2 VOUT1
NOTES 1. EXPOSED PAD SHOULD BE CONNECTED TO AGND. 2. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
AVIN 6 VIN1 7 SW 8 PGND 9 EN1 10
Figure 2. Pin Configuration--View from Top of the Die
Table 8. Preliminary Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TP Mnemonic NC VOUT3 VIN3 EN3 nRSTO AVIN VIN1 SW PGND EN1 VOUT1 WDI2 VIN2 VOUT2 WSTAT EN2 MODE WMOD WDI1 MR AGND Description Do not connect to this pin. LDO2 Output Voltage and Sensing Input. LDO2 Input Supply (1.7 V to 5.5 V). Enable LDO2. EN3 = high: turn on LDO2; EN3 = low: turn off LDO2. Open-Drain Reset Output, Active Low. Regulators Housekeeping and Supervisory Input Supply (2.3 V to 5.5 V). Buck Input Supply (2.3 V to 5.5 V). Buck Switching Node. Dedicated Power Ground for Buck Regulator. Enable Buck. EN1 = high: turn on buck; EN1 = low: turn off buck. Buck Sensing Node. Watchdog 2 (Long Timeout) Refresh Input from Processor. Can be disabled only by factory option. LDO1 Input Supply (1.7 V to 5.5 V). LDO1 Output Voltage and Sensing Input. Open-Drain Watchdog Timeout Status. WSTAT = high: Watchdog 1 timeout or power-on reset; WSTAT = low: Watchdog 2 timeout. Auto cleared after one second. Enable LDO1. EN2 = high: turn on LDO1. EN2 = low: turn off LDO1. Buck Mode. MODE = high: buck regulator operates in fixed PWM mode; MODE = low: buck regulator operates in pulse skipping mode (PSM) at light load and in constant PWM at higher load. Watchdog Mode. WMOD = low: Watchdog 1 normal mode; WMOD = high: Watchdog 1 cannot be disabled by a three-state condition applied on WDI1. Watchdog 1 Refresh Input from Processor. If WDI1 is in high-Z and WMOD is low, Watchdog 1 is disabled. Manual Reset Input, Active Low. Analog Ground (TP = Thermal Pad). Exposed pad should be connected to AGND.
Rev. 0 | Page 8 of 32
08811-002
ADP5042 TYPICAL PERFORMANCE CHARACTERISTICS
VIN1 = VIN2 = VIN3 = AVIN = 5.0 V, TA = 25C, unless otherwise noted.
SW
4
1
VOUT1
2
VOUT2
2
VOUT1
3
VOUT3
EN
1
08811-006
3
08811-003
LOAD
CH1 2.0V/DIV 1M BW 20.0M CH2 2.0V/DIV 1M BW 500M CH3 2.0V/DIV 1M BW 20.0M
A CH1
1.76V
200s/DIV 50.0MS/s 20.0ns/pt
CH1 CH2 CH3 CH4
4.0V/DIV 3.0V/DIV 200mA/DIV 5.0V/DIV
1M BW 20.0M A CH1 1M BW 500M 1M BW 20.0M 1M BW 500M
2.24V
50s/DIV 20.0MS/s 50.0ns/pt
Figure 3. 3-Channel Start-Up Waveforms
1.0 0.9
Figure 6. Buck Startup, VOUT1 = 1.8 V, IOUT2 = 20 mA
3.34
-40C +25C +85C
SYSTEM QUIESCENT CURRENT (mA)
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2.3
2.8 3.3 3.8 4.3 4.8 5.3
3.32
OUTPUT VOLTAGE (V)
VOUT1 = 1.8V, VOUT2 = VOUT = 3.3V
08811-004
3.30
3.28
3.26
3.24
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
INPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Figure 4. System Quiescent Current (Sum of All the Input Currents) vs. Input Voltage, VOUT1 = 1.8 V, VOUT2 = VOUT3 = 3.3 V
Figure 7. Buck Load Regulation Across Temperature, VOUT1 = 3.3 V, Auto Mode
SW
4
1.830 1.825 1.820 -40C +25C +85C
VOUT1
OUTPUT VOLTAGE (V)
2
1.815 1.810 1.805 1.800 1.795 1.790 1.785 1.780 1.775
08811-008
EN
1 3
IIN
08811-005
CH1 CH2 CH3 CH4
2.0V/DIV 2.0V/DIV 100mA/DIV 5.0V/DIV
1M BW 20.0M A CH1 1M BW 500M 1M BW 20.0M 1M BW 500M
2.92V
50s/DIV 50.0MS/s 20.0ns/pt
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
OUTPUT CURRENT (A)
Figure 5. Buck Startup, VOUT1 = 1.8 V, IOUT1 = 20 mA
Figure 8. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V, Auto Mode
Rev. 0 | Page 9 of 32
08811-007
3.22
ADP5042
1.795 1.794 1.793
+85C
100 90 80
3.6V 4.5V 5.5V
OUTPUT VOLTAGE (V)
1.792 1.791 1.790 1.789 1.788 1.787 1.786
08811-009
EFFICIENCY (%)
+25C
70 60 50 40 30 20 10 0 0.001
08811-012
1.785 1.784 0 0.1 0.2
-40C
0.3
0.4
0.5
0.6
0.7
0.8
0.01
0.1
1
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 9. Buck Load Regulation Across Temperature, VOUT1 = 1.8 V, PWM Mode
1.797 1.796
Figure 12. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V, PWM Mode
100 90 80
OUTPUT VOLTAGE (V)
1.795 1.794 1.793
VIN = 5.5V
70
EFFICIENCY (%)
60 50 40 30 20
2.4V 3.6V 4.5V 5.5V
0.001 0.01 0.1 1
VIN = 4.5V
VIN = 3.6V
1.792 1.791 1.790 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
OUTPUT CURRENT (A)
08811-010
10 0 0.0001
0.8
OUTPUT CURRENT (A)
Figure 10. Buck Load Regulation Across Input Voltage, VOUT1 = 1.8 V, PWM Mode
100 90 80 70
Figure 13. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 1.8 V, Auto Mode
100 90 80 70 2.4V 3.6V 4.5V 5.5V
EFFICIENCY (%)
60 50 40 30 20
08811-011
EFFICIENCY (%)
60 50 40 30 20 10 0 0.001
08811-014
10 0 0.0001
3.6V 4.5V 5.5V
0.001 0.01 0.1 1
0.01 IOUT (A)
0.1
1
OUTPUT CURRENT (A)
Figure 11. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V, Auto Mode
Figure 14. Buck Efficiency vs. Load Current, Across Input Voltage, VOUT2 = 1.8 V, PWM Mode
Rev. 0 | Page 10 of 32
08811-013
ADP5042
100 90
1.7 1.6
80 70
60 50 40 30 20 10 0 0.001
08811-015
OUTPUT CURRENT (A)
-40C +25C +85C
1.5 1.4 1.3 1.2 1.1 1.0 2.6
EFFICIENCY (%)
0.01
0.1
1
3.6
4.6 INPUT VOLTAGE (V)
5.6
OUTPUT CURRENT (A)
Figure 15. Buck Efficiency vs. Load Current, Across Temperature, VOUT1 = 1.8 V, PWM Mode
100 90 80
Figure 18. Buck DC Current Capability vs. Input Voltage, VOUT1 = 1.8 V
3.10
-40C +25C +85C
3.05
-40C
FREQUENCY (MHz)
70
+25C
3.00
EFFICIENCY (%)
60 50 40 30 20 10 0 0.0001
08811-016
2.95
+85C
2.90
08811-019
2.85
0.001
0.01
0.1
1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 16. Buck Efficiency vs. Load Current, Across Temperature, VOUT1 = 3.3 V, Auto Mode
100 90 80 70 -40C +25C +85C
Figure 19. Buck Switching Frequency vs. Output Current, Across Temperature, VOUT1 = 1.8 V, PWM Mode
VOUT
1
EFFICIENCY (%)
60 50 40 30 20
08811-017
ISW
2
SW
10 0 0.0001
0.001 0.01 0.1 1
3 B 20.0M CH1 20.0mV/DIV W CH2 200mA/DIV 1M BW 20.0M B 20.0M CH3 2.0V/DIV 1M W
A CH1
2.4mV
5.0s/DIV 20.0MS/s 50.0ns/pt
OUTPUT CURRENT (A)
Figure 17. Buck Efficiency vs. Load Current, Across Temperature, VOUT1 = 1.8 V, Auto Mode
Figure 20. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, Auto Mode
Rev. 0 | Page 11 of 32
08811-020
08811-018
ADP5042
VOUT
2
VIN
ISW
3
VOUT
2
SW
1 3
08811-021
SW
1
CH1 2.0V/DIV 1M BW 20.0M B 20.0M CH2 50.0mV/DIV W B 20.0M CH3 500mA/DIV W
A CH1
1.56mV
5.0s/DIV 200MS/s 5.0ns/pt
B 20.0M CH1 3V/DIV W B 20.0M CH2 50mV/DIV W CH3 900mV/DIV 1M BW 20.0M
A CH3
4.79V
100s/DIV 10.0MS/s 100ns/pt
Figure 21. Typical Waveforms, VOUT1 = 1.8 V, IOUT2 = 30 mA, Auto Mode
Figure 24. Buck Response to Line Transient, Input Voltage from 4.5 V to 5.0 V, VOUT1 = 3.3 V, PWM Mode
VOUT
2
VIN
ISW
3
VOUT
2
SW
SW
3
08811-022
1
4
CH1 2.0V/DIV 1M BW 20.0M B 20.0M CH2 50.0mV/DIV W B 20.0M CH3 500mA/DIV W
4.96mV
100s/DIV 20MS/s 100ns/pt
Figure 22. Typical Waveforms, VOUT1 = 1.8 V, IOUT1 = 30 mA, PWM Mode
Figure 25. Buck Response to Line Transient, VIN = 4.5 V to 5.0 V, VOUT1 = 1.8 V, PWM Mode
1
VOUT
SW
1
2
ISW
VOUT
2
SW
08811-023
3 B 20.0M A CH1 CH1 20.0mV/DIV W CH2 200mA/DIV 1M BW 20.0M CH3 2.0V/DIV 1M BW 20.0M
3
IOUT
Figure 23. Typical Waveforms, VOUT1 = 3.3 V, IOUT2 = 30 mA, PWM Mode
Figure 26. Buck Response to Load Transient, IOUT1 from 1 mA to 50 mA, VOUT1 = 3.3 V, Auto Mode
Rev. 0 | Page 12 of 32
08811-026
2.4mV
200ns/DIV 500MS/s 2.0ns/pt
B 20.0M CH1 4V/DIV W CH2 50mV/DIV 1M BW 20.0M CH3 50mA/DIV 1M BW 20.0M
A CH3
44mA
200s/DIV 10MS/s 100ns/pt
08811-025
A CH1
1.56mV
500ns/DIV 200MS/s 5.0ns/pt
B 20.0M A CH3 CH2 50mV/DIV W CH3 1V/DIV 1M BW 20.0M CH4 2V/DIV 1M BW 20.0M
08811-024
ADP5042
SW
1 3
IIN
VOUT
2
VOUT
1
VOUT
LOAD
3
2
EN
B 20.0M CH1 4V/DIV W B 20.0M CH2 50mV/DIV W CH3 50mA/DIV 1M BW 20.0M
Figure 27. Buck Response to Load Transient, IOUT2 from 1 mA to 50 mA, VOUT2 = 1.8 V, Auto Mode
08811-027
Figure 30. LDO1 Startup, VOUT3=1.5 V, IOUT3 = 5 mA
SW
1
3
IIN
VOUT
2
1
VOUT
LOAD
3
2
EN
Figure 28. Buck Response to Load Transient, IOUT1 from 20 mA to 140 mA, VOUT1 = 3.3 V, Auto Mode
1.510
08811-028
B 20.0M A CH3 CH1 4V/DIV W B 20.0M CH2 50mV/DIV W CH3 50mA/DIV 1M BW 20.0M
Figure 31. LDO2 Startup, VOUT3=3.3 V, IOUT3 = 5 mA
SW
2
1.508
VOUT1
3
LOAD
4
OUTPUT VOLTAGE (V)
1.506
1.504
1.502
08811-029
0.001
0.01
0.1
OUTPUT CURRENT (A)
Figure 29. Buck Response to Load Transient, IOUT2 from 20 mA to 180 mA, VOUT1 = 1.8 V, PWM Mode
Figure 32. LDO1 Load Regulation Across Input Voltage, VOUT2 = 1.5 V
Rev. 0 | Page 13 of 32
08811-032
CH2 4V/DIV 1M BW 20.0M A CH3 CH3 50mV/DIV 1M BW 20.0M CH4 50mA/DIV 1M BW 20.0M
145mA
200s/DIV 50MS/s 20ns/pt
1.500 0.0001
3.3V 4.5V 5.0V 5.5V
08811-031
86mA
200s/DIV 10MS/s 100ns/pt
CH1 1V/DIV 1M BW 500M A CH2 CH2 3V/DIV 1M BW 500M CH3 50mA/DIV 1M BW 20.0M
1.14V
100s/DIV 1MS/s 1.0s/pt
08811-030
A CH3
28mA
200s/DIV 5MS/s 200ns/pt
CH1 1V/DIV 1M BW 500M A CH2 CH2 3V/DIV 1M BW 500M CH3 50mA/DIV 1M BW 20.0M
1.14V
50s/DIV 2MS/s 500ns/pt
ADP5042
1.53 +85C +25C -40C 1.52
3.35 3.34 3.33
+85C +25C -40C
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
08811-033
1.51
3.32 3.31 3.30 3.29 3.28 3.27 3.26
1.5
1.49
1.48
0.001
0.01
0.1
0.001
0.01
0.1
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 33. LDO1 Load Regulation Across Temperature, VIN2 = 3.3 V, VOUT2 = 1.5 V
1.520 1.515 1.510
100A 1mA 10mA 100mA 150mA
Figure 36. LDO2 Load Regulation Across Temperature, VIN3 = 3.6 V, VOUT3 = 3.3 V
3.325 3.320 3.315
100A 1mA 10mA 100mA 150mA
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.505 1.500 1.495 1.490 1.485 1.480
3.310 3.305 3.300 3.295 3.290 3.285
08811-034
3.6
4.5
5.0
5.5
3.6
4.5
5.0
5.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 34. LDO1 Line Regulation Across Output Load, VOUT2 = 1.5 V
3.35 3.34 3.33 3.6V 4.5V 5.0V 5.5V
Figure 37. LDO2 Line Regulation Across Output Load, VOUT3 = 3.3 V
250
200
OUTPUT VOLTAGE (V)
3.32 3.31 3.30 3.29 3.28 3.27 3.26
50
CURRENT (A)
150
100
0
0.05 LOAD (A)
0.10
0.15
OUTPUT CURRENT (A)
Figure 35. LDO2 Load Regulation Across Input Voltage, VOUT3 = 3.3 V
Figure 38. LDO2 Ground Current vs. Output Load, VOUT3 = 2.8 V
Rev. 0 | Page 14 of 32
08811-038
0.001
0.01
0.1
08811-035
3.25 0.0001
0
08811-037
3.280
08811-036
1.47 0.0001
3.25 0.0001
ADP5042
0.50 0.45 0.40
1A 100A 1mA 10mA 100mA 150mA
VIN
GROUND CURRENT (mA)
0.35 0.30 0.25
1 2
VOUT
0.20 0.15 0.10
08811-042
0.05
2.8 3.3 3.8 4.3 4.8 5.3 5.8
08811-039
2
0 2.3
INPUT VOLTAGE (V)
B 20.0M CH1 10.0mV/DIV W CH2 800mV/DIV 1M BW 20.0M
A CH2
5.33V
Figure 39. LDO2 Ground Current vs. Input Voltage, Across Output Load, VOUT3 = 2.8 V
Figure 42. LDO2 Response to Line Transient, Input Voltage from 4.5 V to 5.5 V, VOUT3 = 3.3 V
VIN
3
IOUT
1 2
VOUT
1
VOUT
A CH3
28mA
200s/DIV 500kS/s 2.0s/pt
08811-040
CH1 50mV/DIV 1M BW 500M CH3 50mA/DIV 1M BW 20.0M
B 20.0M CH1 10.0mV/Div W CH2 800mV/Div 1M BW 20.0M
A CH2
5.33V
Figure 40. LDO2 Response to Load Transient, IOUT3 from 1 mA to 80 mA, VOUT3 = 3.3 V
Figure 43. LDO1 Line Transient VIN = 4.5 V to 5.5 V, VOUT2 = 1.5 V
3.0
2.5
OUTPUT VOLTAGE (V)
2.0
3
IOUT
1.5
1.0
1
VOUT
0.5 5.5V 4.5V 3.6V
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
08811-056
0
08811-041
CH1 50mV/DIV 1M W 500M A CH3 CH3 50mA/DIV 1M BW 20.0M
B
50mA
200s/DIV 500kS/s 2.0s/pt
LOAD CURRENT (A)
Figure 41. LDO1 Response to Load Transient, IOUT3 from 1 mA to 80 mA, VOUT2 = 1.5 V
Figure 44. LDO1, LDO2 Output Current Capability vs. Input Voltage
Rev. 0 | Page 15 of 32
08811-043
2
ADP5042
100 VOUT3 = 3.3V, VIN3 = 3.6V, VOUT3 = 1.5V, VIN3 = 1.8V, VOUT3 = 2.8V, VIN3 = 3.1V, ILOAD = 300mA ILOAD = 300mA ILOAD = 300mA
10
RMS NOISE (V)
100
NOISE (V/Hz)
CH2; VOUT = 3.3V; CH2; VOUT = 3.3V; CH2; VOUT = 2.8V; CH2; VOUT = 1.5V; CH2; VOUT = 1.5V; 0.001 0.01 0.1 1 LOAD (mA) 10 VIN = 5V VIN = 3.6V VIN = 3.1V VIN = 5V VIN = 1.8V
08811-044
1
0.1
100
1k
1
10
100 1k 10k FREQUENCY (Hz)
100k
1M
Figure 45. LDO1 Output Noise vs. Load Current, Across Input and Output Voltage
Figure 48. LDO2 Noise Spectrum Across Output Voltage, VIN = VOUT + 0.3 V
100
VOUT2 = 3.3V, VIN2 = 3.6V, ILOAD = 300mA VOUT3 = 3.3V, VIN3 = 3.6V, ILOAD = 300mA VOUT2 = 1.5V, VIN2 = 1.8V, ILOAD = 300mA
10
RMS NOISE (V)
100
NOISE (V/Hz)
1.0
0.1
CH3; VOUT CH3; VOUT CH3; VOUT CH3; VOUT CH3; VOUT 0.001 0.01 0.1 1 LOAD (mA) = 3.3V; VIN = 5V = 3.3V; VIN = 3.6V = 2.8V; VIN = 3.1V = 1.5V; VIN = 5V = 1.5V; VIN = 1.8V
08811-045
10
100
1k
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
Figure 46. LDO2 Output Noise vs. Load Current, Across Input and Output Voltage
100
Figure 49. LDO1 vs. LDO2 Noise spectrum
VOUT2 = 3.3V, VIN2 = 3.6V, ILOAD = 300mA VOUT2 = 1.5V, VIN2 = 1.8V, ILOAD = 300mA VOUT2 = 2.8V, VIN2 = 3.1V, ILOAD = 300mA
-10 -20 -30 1mA 10mA 100mA 200mA 300mA
10
NOISE (V/Hz)
-40 1.0
PSRR (dB)
-50 -60 -70 -80 -90
08811-049
0.1
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
08811-046
0.01 10
-100 10
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
Figure 47. LDO1 Noise Spectrum Across Output Voltage, VIN = VOUT + 0.3 V
Figure 50. LDO2 PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 2.8 V
Rev. 0 | Page 16 of 32
08811-048
10 0.0001
0.01 10
VOUT3 = 1.5V, VIN3 = 1.8V, ILOAD = 300mA VOUT2 = 2.8V, VIN2 = 3.1V, ILOAD = 300mA VOUT3 = 2.8V, VIN3 = 3.1V, ILOAD = 300mA
08811-055
10 0.0001
0.01
ADP5042
-10 -20 -30 -40 1mA 10mA 100mA 200mA 300mA -10 -20 -30 -40 1mA 10mA 100mA 200mA 300mA
PSRR (dB)
PSRR (dB)
-50 -60 -70 -80 -90
08811-050
-50 -60 -70 -80 -90
08811-053 08811-054
-100 10
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
-100 10
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
Figure 51. LDO2 PSRR Across Output Load, VIN3 = 3.1 V, VOUT3 = 2.8 V
-10 -20 -30 -40 1mA 10mA 100mA 200mA
Figure 54. LDO1 PSRR Across Output Load, VIN2 = 5.0 V, VOUT2 = 1.5 V
-10 -20 -30 -40 1mA 10mA 100mA 200mA 300mA
PSRR (dB)
PSRR (dB)
08811-051
-50 -60 -70 -80 -90 -100 10
-50 -60 -70 -80 -90 -100 10
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
Figure 52. LDO2 PSRR Across Output Load, VIN3 = 5 V, VOUT3 = 3.3 V
Figure 55. LDO1 PSRR Across Output Load, VIN2 = 1.8 V, VOUT2 = 1.5 V
-10 -20 -30 -40 1mA 10mA 100mA 200mA 300mA
PSRR (dB)
-50 -60 -70 -80 -90
08811-052
-100 10
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
Figure 53. LDO2 PSRR Across Output Load, VIN3 = 3.6 V, VOUT3 = 3.3 V
Rev. 0 | Page 17 of 32
ADP5042 THEORY OF OPERATION
VOUT1 MR WMOD WDI1 WDI2 40k ENWD1 VDDA GM ERROR AMP PWM COMP VIN1 ILIMIT PSM COMP PWM/ PSM CONTROL BUCK1 R0 VDDA R1 SOFT START 52k WATCHDOG DETECTOR1 200k WATCHDOG STATUS MONITOR WSTAT WATCHDOG DETECTOR2 ENWD2 60 ENBK AVIN VDDA
POFF
DEBOUNCE
LOW CURRENT SW
A B C D Y RESET GENERATOR VREF
nRSTO
OSCILLATOR DRIVER AND ANTISHOOT THROUGH PGND POFF MODE EN1 EN2 EN3 ENABLE AND MODE CONTROL SEL MODE ENBK ENLDO1 ENLDO2 VDDA OPMODE_FUSES R2 500 ENLDO1 R4 LDO1 CONTROL R1 VDDA LDO2 CONTROL R3 SYSTEM UNDERVOLTAGE LOCK OUT THERMAL SHUTDOWN ENLDO2
500
ADP5042
VIN2 AGND VOUT2 VIN3
VOUT3
Figure 56. Functional Block Diagram
POWER MANAGEMENT UNIT
The ADP5042 is a micro power management unit (micro PMU) combing one step-down (buck) dc-to-dc convertor, two low dropout linear regulators (LDOs), and a supervisory circuit, with dual watchdog, for processor control. The regulators are activated by a logic level high applied to the respective EN pin. The EN1 controls the buck regulator, the EN2 controls LDO1, and the EN3 controls LDO2. The ADP5042 has factory programmed output voltages and reset voltage threshold. Other features available in this device are the mode pin to control the buck switching operation, a status pin informing the external processor which watchdog caused a reset and push-button reset input. When a regulator is turned on, the output voltage is controlled through a soft start circuit to avoid a large inrush current due to the discharged output capacitors.
The buck regulator can operate in forced PWM mode if the MODE pin is at a logic high level. In forced PWM mode, the switching frequency of the buck is always constant and does not change with the load current. If the MODE pin is at logic low level, the switching regulator operates in auto PWM/PSM mode. In this mode, the regulator operates at fixed PWM frequency when the load current is above the power saving current threshold. When the load current falls below the power saving current threshold, the regulator enters power saving mode, where the switching occurs in bursts. The burst repetition is a function of the current load and the output capacitor value. This operating mode reduces the switching and quiescent current losses.
Rev. 0 | Page 18 of 32
08811-057
ADP5042
Thermal Protection
In the event that the junction temperature rises above 150C, the thermal shutdown circuit turns off the buck and the LDOs. Extreme junction temperatures can be the result of high current operation, poor circuit board design, or high ambient temperature. A 20C hysteresis is included so that when thermal shutdown occurs, the buck and LDOs do not return to operation until the on-chip temperature drops below 130C. When coming out of thermal shutdown, soft start is initiated.
PWM Mode
In PWM mode, the buck operates at a fixed frequency of 3 MHz, set by an internal oscillator. At the start of each oscillator cycle, the PFET switch is turned on, sending a positive voltage across the inductor. Current in the inductor increases until the current sense signal crosses the peak inductor current threshold that turns off the PFET switch and turns on the NFET synchronous rectifier. This sends a negative voltage across the inductor, causing the inductor current to decrease. The synchronous rectifier stays on for the rest of the cycle. The buck regulates the output voltage by adjusting the peak inductor current threshold.
Undervoltage Lockout
To protect against battery discharge, undervoltage lockout (UVLO) circuitry is integrated in the system. If the input voltage on AVIN drops below a typical 2.15 V UVLO threshold, all channels shut down. In the buck channel, both the power switch and the synchronous rectifier turn off. When the voltage on AVIN rises above the UVLO threshold, the part is enabled once more. Alternatively, the user can select device models with a UVLO set at a higher level, suitable for 5 V applications. For these models, the device hits the turn-off threshold when the input supply drops to 3.65 V typical.
Power Save Mode (PSM)
The buck smoothly transitions to PSM operation when the load current decreases below the PSM current threshold. When the buck enters power save mode, an offset is induced in the PWM regulation level, which makes the output voltage rise. When the output voltage reaches a level that is approximately 1.5% above the PWM regulation level, PWM operation is turned off. At this point, both power switches are off, and the buck enters an idle mode. The output capacitor discharges until the output voltage falls to the PWM regulation voltage, at which point the device drives the inductor to make the output voltage rise again to the upper threshold. This process is repeated while the load current is below the PSM current threshold.
Enable/Shutdown
The ADP5042 has individual control pins for each regulator. A logic level high applied to the ENx pin activates a regulator, a logic level low turns off a regulator. When regulators are turned off after a Watchdog 2 event (see the Watchdog 2 Input section), the reactivation of the regulator occurs with a factory programmed order (see Table 9). The delay between the regulator activation (tD1, tD2) is 2 ms. Table 9. ADP5042 Regulators Sequencing
REGSEQ[1:0] 0 0 0 1 1 0 1 1 Regulators Sequence (First to Last) LDO1 LDO2 Buck Buck LDO1 LDO2 LDO1 Buck LDO2 No sequence, all regulators start at same time
PSM Current Threshold
The PSM current threshold is set to 100 mA. The buck employs a scheme that enables this current to remain accurately controlled, independent of input and output voltage levels. This scheme also ensures that there is very little hysteresis between the PSM current threshold for entry to and exit from the PSM. The PSM current threshold is optimized for excellent efficiency over all load currents.
Short-Circuit Protection
The buck includes frequency foldback to prevent output current runaway on a hard short. When the voltage at the feedback pin falls below half the target output voltage, indicating the possibility of a hard short at the output, the switching frequency is reduced to half the internal oscillator frequency. The reduction in the switching frequency allows more time for the inductor to discharge, preventing a runaway of output current.
BUCK SECTION
The buck uses a fixed frequency and high speed current mode architecture. The buck operates with an input voltage of 2.3 V to 5.5 V.
Control Scheme
The buck operates with a fixed frequency, current mode PWM control architecture at medium to high loads for high efficiency but shift to a power save mode (PSM) control scheme at light loads to lower the regulation power losses. When operating in fixed frequency PWM mode, the duty cycle of the integrated switches is adjusted and regulates the output voltage. When operating in PSM at light loads, the output voltage is controlled in a hysteretic manner, with higher output voltage ripple. During part of this time, the converter is able to stop switching and enters an idle mode, which improves conversion efficiency.
Soft Start
The buck has an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. This prevents possible input voltage drops when a battery or a high impedance power source is connected to the input of the converter.
Current Limit
The buck has protection circuitry to limit the amount of positive current flowing through the PFET switch and the amount of negative current flowing through the synchronous rectifier. The positive current limit on the power switch limits
Rev. 0 | Page 19 of 32
ADP5042
the amount of current that can flow from the input to the output. The negative current limit prevents the inductor current from reversing direction and flowing out of the load.
Reset Output
The ADP5042 has an active-low, open-drain reset output. This output structure requires an external pull-up resistor to connect the reset output to a voltage rail that is no higher than 6 V. The resistor should comply with the logic low and logic high voltage level requirements of the microprocessor while supplying input current and leakage paths on the nRSTO pin. A 10 k resistor is adequate in most situations. The reset output is asserted when the monitored rail is below the reset threshold (VTH), when WDI1 or WDI2 is not serviced within the watchdog timeout period (tWD1 and tWD12). Reset remains asserted for the duration of the reset active timeout period (tRP) after VCC rises above the reset threshold or after the watchdog timer times out. Figure 57 illustrates the behavior of the reset output, nRSTO, and it assumes that VOUT2 is selected as the rail to be monitored and supplies the external pull-up connected to the nRSTO output.
VOUT2 VOUT2 1V 0V VOUT2 nRSTO 0V RSTO VTH VTH
100% Duty Operation
With a dropping input voltage or with an increase in load current, the buck may reach a limit where, even with the PFET switch on 100% of the time, the output voltage drops below the desired output voltage. At this limit, the buck transitions to a mode where the PFET switch stays on 100% of the time. When the input conditions change again and the required duty cycle falls, the buck immediately restarts PWM regulation without allowing overshoot on the output voltage.
LDO SECTION
The ADP5042 contains two LDOs with low quiescent current, low dropout linear regulator, and provides up to 300 mA of output current. Drawing a low 15 A quiescent current (typical) at no load makes the LDO ideal for battery-operated portable equipment. The LDO operates with an input voltage range of 1.7 V to 5.5 V. The wide operating range makes these LDOs suitable for cascading configurations where the LDO supply voltage is provided from the buck regulator. The LDOs also provide high power supply rejection ratio (PSRR), low output noise, and excellent line and load transient response with just a small 1 F ceramic input and output capacitor. LDO2 is optimized to supply analog circuits because it offers better noise performance compared to LDO1. LDO1 should be used in applications where noise performance is not critical. Internally, one LDO consists of a reference, an error amplifier, a feedback voltage divider, and a PMOS pass transistor. Output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to flow and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, reducing the current flowing to the output.
tRP1
tRD
1V 0V
tRP1
tRD
Figure 57. Reset Timing Diagram
The reset threshold voltage and the sensed rail (VOUT1, VOUT2, VOUT3, or AVIN) are factory programmed. Refer to Table 15 for a complete list of the reset thresholds available for the ADP5042. When monitoring the input supply voltage, AVIN, if the selected reset threshold is below the UVLO level (factory programmable to 2.25 V or 3.6 V) the reset output, nRSTO, is asserted low as soon as the input voltage falls below the UVLO threshold. Below the UVLO threshold, the reset output is maintained low down to ~1 V VIN. This it to ensure that the reset output is not released when there is sufficient voltage on the rail supplying a processor to restart the processor operations.
Manual Reset Input
The ADP5042 features a manual reset input (MR) which, when driven low, asserts the reset output. When MR transitions from low to high, reset remains asserted for the duration of the reset active timeout period before deasserting. The MR input has a 52 k, internal pull-up, connected to AVIN, so that the input is always high when unconnected. An external push-button switch can be connected between MR and ground so that the user can generate a reset. Debounce circuitry for this purpose is integrated on chip. Noise immunity is provided on the MR input, and fast, negative-going transients of up to 100 ns (typical) are ignored. A 0.1 F capacitor between MR and ground provides additional noise immunity.
SUPERVISORY SECTION
The ADP5042 provides microprocessor supply voltage supervision by controlling the reset input of the microprocessor. Code execution errors are avoided during power-up, powerdown, and brownout conditions by asserting a reset signal when the supply voltage is below a preset threshold and by allowing supply voltage stabilization with a fixed timeout reset pulse after the supply voltage rises above the threshold. In addition, problems with microprocessor code execution can be monitored and corrected with a dual-watchdog timer.
Rev. 0 | Page 20 of 32
08811-058
ADP5042
Watchdog 1 Input
The ADP5042 features a watchdog timer that monitors microprocessor activity. A timer circuit is cleared with every low-tohigh or high-to-low logic transition on the watchdog input pin (WDI1), which detects pulses as short as 80 ns. If the timer counts through the preset watchdog timeout period (tWD1), reset is asserted. The microprocessor is required to toggle the WDI1 pin to avoid being reset. Failure of the microprocessor to toggle WDI1 within the timeout period, therefore, indicates a code execution error, and the reset pulse generated restarts the microprocessor in a known state. As well as logic transitions on WDI1, the watchdog timer is also cleared by a reset assertion due to an undervoltage condition on the monitored rail. When reset is asserted, the watchdog timer is cleared and does not begin counting again until reset deasserts. Watchdog 1 timer can be disabled by leaving WDI1 floating or by three-stating the WDI1 driver. The pin WMOD controls the Watchdog 1 operating mode. If WMOD is set to logic level low, Watchdog 1 is enabled as long as WDI1 is not in three-state. If WMOD is set to logic level high, Watchdog 1 is always active and cannot be disabled by a three-state condition. WMOD input has an internal 200 k pull-down resistor. Watchdog 1 timeout is factory set to two possible values as indicated in Table 17.
VSENSED
1V 0V
nRSTO
VTH
tRP1 0V
tWD1
tRP1
08811-059
WDI1
0V
Figure 58. Watchdog 1 Timing Diagram
Watchdog 2 Input
The ADP5042 features an additional watchdog timer that monitors microprocessor activity in parallel to the first watchdog with a much longer timeout. This provides additional security and safety in case Watchdog 1 is incorrectly strobed. A timer circuit is cleared with every low-to-high or high-to-low logic transition on the watchdog input pin (WDI2), which detects pulses as short as 8 s. If the timer counts through the preset watchdog timeout period (tWD2), reset is asserted, followed by a power cycle of all regulators . The microprocessor is required to toggle the WDI2 pin to avoid being reset and powered down. Failure of the microprocessor to toggle WDI2 within the timeout period, therefore, indicates a code execution error, and the reset output nRSTO is forced low for tRP2. Then, all the regulators are turned off for the tPOFF time. After the tPOFF period, the regulators are reactivated according to a predefined sequence (see Table 9). Finally, the reset line (nRSTO) is asserted for tRP1. This guarantees a clean power-up of the system and proper reset. As well as logic transitions on WDI2, the watchdog timer is also cleared by a reset assertion due to an undervoltage condition on the VTH monitored rail which can be factory programmable between VOUT1, VOUT2, VOUT3, and AVIN (see Table 20). When reset is asserted, the watchdog timer is cleared and does not begin counting again until reset deasserts. Watchdog 2 timeout is factory set to seven possible values as indicated in Table 18. One additional option allows Watchdog 2 to be factory disabled.
AVIN/VINx/ENx
tPOFF VOUT1
0V
tD1 tD2 VTH
tD1 tD2
VOUT3
0V
VOUT2
0V
nRSTO 0V
WDI2
tRP1
tWD2
tRP2
tRP1
0V
tWDCLEAR
WSTAT
08811-060
Figure 59. Watchdog 2 Timing Diagram (Assuming That VOUT2 Is the Monitored Rail)
Rev. 0 | Page 21 of 32
ADP5042
Watchdog Status Indicator
In addition to the dual watchdog function, the ADP5042 features a watchdog status monitor available on the WSTAT pin. This pin can be queried by the external processor to determine the origin of a reset. WSTAT is an open-drain output. WSTAT outputs a logic level depending on the condition that has generated a reset. WSTAT is forced low if the reset was generated because of a Watchdog 2 timeout. WSTAT is pulled high, through external pull-up, for any other reset cause (Watchdog 1 timeout, power failure or monitored voltage below threshold). The status monitor is automatically cleared (set to logic level high) 10 seconds after the nRSTO low to high transition (tWDCLEAR), processor firmware must be designed being able to read the WSTAT flag before tWDCLEAR expiration after a Watchdog 2 reset. The WSTAT flag is not updated in the event of a reset due to a low voltage threshold detection or Watchdog 1 event occurring within 10 seconds after nRSTO low to high transition. In this situation, WSTAT maintains the previous state (see state flow in Figure 60). The external processor can further distinguish a reset caused by a Watchdog 1 timeout from a power failure, status monitor WSTAT indicating a high level, by implementing a RAM check or signature verification after reset. A RAM check or signature failure indicates that a power failure has occurred, whereas a RAM check or signature validation indicates that a Watchdog 1 timeout has occurred. Table 10 shows the possible watchdog decoded statuses. Table 10. Watchdog Status Decoding
WSTAT High High Low RAM CHECKSUM Failed Ok Don't care RESET ORIGIN Power failure Watchdog 1 Watchdog 2
NO POWER APPLIED TO AVIN. ALL REGULATORS AND SUPERVISORY TURNED OFF
NO POWER
AVIN > VUVLO AVIN < VUVLO TRANSITION STATE
POR
AVIN < VUVLO INTERNAL CIRCUIT BIASED REGULATORS AND SUPERVISORY NOT ACTIVATED
END OF POR
STANDBY
AVIN < VUVLO
ALL ENx = HIGH AVIN < VUVLO TRANSITION STATE
ALL ENx = LOW
WSTAT TIMEOUT (tWDCLEAR ) WDOG2 TIMEOUT (tWD2)
TRANSITION STATE WSTAT = 0 WSTAT = LOW
WSTAT = HIGH
WSTAT = 1 ACTIVE WDOG1 TIMEOUT (tWD1) AND WSTAT TIMEOUT WDOG1 TIMEOUT (tWD1) WSTAT = HIGH VMON < VTH WSTAT = 1
08811-061
ALL REGULATORS AND SUPERVISOR ACTIVATED
RESET SHORT
TRANSITION STATE
END OF RESET PULSE (tRP1 )
END OF RESET PULSE (tRP2 )
POWER OFF
RESET NORMAL
END OF (tPOFF) PULSE
Figure 60. ADP5042 State Flow
Rev. 0 | Page 22 of 32
ADP5042 APPLICATIONS INFORMATION
BUCK EXTERNAL COMPONENT SELECTION
Trade-offs between performance parameters such as efficiency and transient response can be made by varying the choice of external components in the applications circuit, as shown in Figure 66.
Output Capacitor
Higher output capacitor values reduce the output voltage ripple and improve load transient response. When choosing this value, it is also important to account for the loss of capacitance due to output voltage dc bias. Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any dc-to-dc converter because of their poor temperature and dc bias characteristics. The worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage is calculated using the following equation: CEFF = COUT x (1 - TEMPCO) x (1 - TOL) where: CEFF is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. In this example, the worst-case temperature coefficient (TEMPCO) over -40C to +85C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and COUT is 9.2481 F at 1.8 V, as shown in Figure 61. Substituting these values in the equation yields CEFF = 9.2481 F x (1 - 0.15) x (1 - 0.1) = 7.0747 F To guarantee the performance of the buck, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application.
12
Inductor
The high switching frequency of the ADP5042 buck allows for the selection of small chip inductors. For best performance, use inductor values between 0.7 H and 3 H. Suggested inductors are shown in Table 11. The peak-to-peak inductor current ripple is calculated using the following equation:
I RIPPLE =
VOUT x (VIN - VOUT ) VIN x f SW x L
where: fSW is the switching frequency. L is the inductor value. The minimum dc current rating of the inductor must be greater than the inductor peak current. The inductor peak current is calculated using the following equation:
I PEAK = I LOAD( MAX ) +
I RIPPLE 2
Inductor conduction losses are caused by the flow of current through the inductor, which has an associated internal dc resistance (DCR). Larger sized inductors have smaller DCR, which may decrease inductor conduction losses. Inductor core losses are related to the magnetic permeability of the core material. Because the buck is high switching frequency dc-to-dc converters, shielded ferrite core material is recommended for its low core losses and low EMI. Table 11. Suggested 1.0 H Inductors
Vendor Murata Murata Taiyo Yuden Coilcraft TDK Coilcraft Toko Model LQM2MPN1R0NG0B LQM18FN1R0M00B CBMF1608T1R0M EPL2014-102ML GLFR1608T1R0M-LR 0603LS-102 MDT2520-CN Dimensions (mm) 2.0 x 1.6 x 0.9 1.6 x 0.8 x 0.8 1.6 x 0.8 x 0.8 2.0 x 2.0 x 1.4 1.6 x 0.8 x 0.8 1.8 x 1.69 x 1.1 2.5 x 2.0 x 1.2 ISAT (mA) 1400 150 290 900 230 400 1350 DCR (m) 85 26 90 59 80 81 85
10
CAPACITANCE (F)
8
6
4
2
0
1
2
3
4
5
6
DC BIAS VOLTAGE (V)
Figure 61. Typical Capacitor Performance
Rev. 0 | Page 23 of 32
08811-062
0
ADP5042
The peak-to-peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation:
Input Capacitor
Higher value input capacitors help to reduce the input voltage ripple and improve transient response. Maximum input capacitor current is calculated using the following equation:
VRIPPLE =
I RIPPLE V IN = (2 x f SW ) x 2 x L x C OUT 8 x f SW x C OUT
Capacitors with lower equivalent series resistance (ESR) are preferred to guarantee low output voltage ripple, as shown in the following equation:
I CIN I LOAD ( MAX )
VOUT (VIN - VOUT ) VIN
ESRCOUT
VRIPPLE I RIPPLE
To minimize supply noise, place the input capacitor as close to the VIN pin of the buck as possible. As with the output capacitor, a low ESR capacitor is recommended. The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 3 F and a maximum of 10 F. A list of suggested capacitors is shown in Table 13. Table 13. Suggested 4.7 F Capacitors
Voltage Rating (V) 6.3 6.3 6.3
The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 7 F and a maximum of 40 F. Table 12. Suggested 10 F Capacitors
Vendor Murata Taiyo Yuden TDK Panasonic Type X5R X5R X5R X5R Model GRM188R60J106 JMK107BJ475 C1608JB0J106K ECJ1VB0J106M Case Size 0603 0603 0603 0603 Voltage Rating (V) 6.3 6.3 6.3 6.3
Vendor Murata Taiyo Yuden Panasonic
Type X5R X5R X5R
Model GRM188R60J475ME19D JMK107BJ475 ECJ-0EB0J475M
Case Size 0603 0603 0402
LDO CAPACITOR SELECTION
Output Capacitor
The ADP5042 LDOs are designed for operation with small, space-saving ceramic capacitors, but they function with most commonly used capacitors as long as care is taken with the ESR value. The ESR of the output capacitor affects stability of the LDO control loop. A minimum of 0.70 F capacitance with an ESR of 1 or less is recommended to ensure stability of the ADP5042. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP5042 to large changes in load current.
The buck regulator requires 10 F output capacitors to guarantee stability and response to rapid load variations and to transition in and out the PWM/PSM modes. In certain applications, where the buck regulator powers a processor, the operating state is known because it is controlled by software. In this condition, the processor can drive the MODE pin according to the operating state; consequently, it is possible to reduce the output capacitor from 10 F to 4.7 F because the regulator does not expect a large load variation when working in PSM mode (see Figure 62).
RFLT 30
ADP5042
AVIN MICRO PMU SW VIN1 C2 4.7F VIN2 C1 1F VIN3 C3 1F WDI MODE ENx 3 GPIO[x:y] L1 1H C6 4.7F PROCESSOR VCORE
VOUT1 VIN 2.3V TO 5.5V PGND VOUT2 C4 1F nRSTO
Input Bypass Capacitor
Connecting a 1 F capacitor from VIN2 and VIN3 to GND reduces the circuit sensitivity to printed circuit board (PCB) layout, especially when long input traces or high source impedance is encountered. If greater than 1 F of output capacitance is required, increase the input capacitor to match it. Table 10. Suggested 1.0 F Capacitors
Vendor Murata TDK Panasonic Taiyo Yuden Type Model Case Size 0402 0402 0402 0402 Voltage Rating (V) 10.0 6.3 6.3 10.0
VDDIO R1 100k RESET GPIO1 GPIO2
VOUT3 C5 1F
VANA
08811-063
X5R
X5R X5R X5R
GRM155R61A105ME15
C1005JB0J105KT ECJ0EB0J105K LMK105BJ105MV-F
ANALOG SUB-SYSTEM
Figure 62. Processor System Power Management with PSM/PWM Control
Rev. 0 | Page 24 of 32
ADP5042
Input and Output Capacitor Properties
Use any good quality ceramic capacitors with the ADP5042 as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with a different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions. X5R or X7R dielectrics with a voltage rating of 6.3 V or 10 V are recommended for best performance. Y5V and Z5U dielectrics are not recommended for use with any LDO because of their poor temperature and dc bias characteristics. Figure 63 depicts the capacitance vs. voltage bias characteristic of a 0402 1 F, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is about 15% over the -40C to +85C temperature range and is not a function of package or voltage rating.
1.2
To guarantee the performance of the ADP5042, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application.
SUPERVISORY SECTION
Watchdog 1 Input Current
To minimize watchdog input current (and minimize overall power consumption), leave WDI1 low for the majority of the watchdog timeout period. When driven high, WDI1 can draw as much as 25 A. Pulsing WDI1 low-to-high-to-low at a low duty cycle reduces the effect of the large input current. When WDI1 is unconnected and WMOD is set to logic level low, a window comparator disconnects the watchdog timer from the reset output circuitry so that reset is not asserted when the watchdog timer times out.
Negative-Going VCC Transients
To avoid unnecessary resets caused by fast power supply transients, the ADP5042 is equipped with glitch rejection circuitry. The typical performance characteristic in Figure 64 plots the monitored rail voltage, VTH , transient duration vs. the transient magnitude. The curve shows combinations of transient magnitude and duration for which a reset is not generated for a 2.93 V reset threshold part. For example, with the 2.93 V threshold, a transient that goes 100 mV below the threshold and lasts 8 s typically does not cause a reset, but if the transient is any larger in magnitude or duration, a reset is generated.
1000 900 800
1.0
CAPACITANCE (F)
0.8
0.6
0.4
0.2
TRANSIENT DURATION (s)
700 600 500 400 300 200 100
08811-065
0
1
2 3 4 DC BIAS VOLTAGE (V)
5
6
Figure 63. Capacitance vs. Voltage Characteristic
Use the following equation to determine the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage. CEFF = CBIAS x (1 - TEMPCO) x (1 - TOL) where: CBIAS is the effective capacitance at the operating voltage. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. In this example, the worst-case temperature coefficient (TEMPCO) over -40C to +85C is assumed to be 15% for an X5R dielectric. The tolerance of the capacitor (TOL) is assumed to be 10%, and CBIAS is 0.94 F at 1.8 V as shown in Figure 63. Substituting these values into the following equation yields: CEFF = 0.94 F x (1 - 0.15) x (1 - 0.1) = 0.719 F Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage.
08811-064
0
0 0.1
1 10 COMPARATOR OVERDRIVE (% OF VTH)
100
Figure 64. Maximum VTH Transient Duration vs. Reset Threshold Overdrive
Watchdog Software Considerations
In implementing the watchdog strobe code of the microprocessor, quickly switching WDI1 low to high and then high to low (minimizing WDI1 high time) is desirable for current consumption reasons. However, a more effective way of using the watchdog function can be considered. A low-to-high-to-low WDI1 pulse within a given subroutine prevents the watchdog from timing out. However, if the subroutine becomes stuck in an infinite loop, the watchdog cannot detect this because the subroutine continues to toggle WDI1. A more effective coding scheme for detecting this error involves
Rev. 0 | Page 25 of 32
ADP5042
using a slightly longer watchdog timeout. In the program that calls the subroutine, WDI1 is set high. The subroutine sets WDI1 low when it is called. If the program executes without error, WDI1 is toggled high and low with every loop of the program. If the subroutine enters an infinite loop, WDI1 is kept low, the watchdog times out, and the microprocessor is reset (see Figure 65).
START
VCC VIN1 VOUT1 VOUT2 nRSTO WDI1 WDI2
VCORE VDDIO RESET I/O I/O MICROPROCESSOR
08811-067
ADP5042
Figure 66. Typical Applications Circuit
SET WDI HIGH RESET
PCB LAYOUT GUIDELINES
Poor layout can affect ADP5042 performance, causing electromagnetic interference (EMI) and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines: *
08811-066
PROGRAM CODE INFINITE LOOP: WATCHDOG TIMES OUT
SUBROUTINE SET WDI LOW
RETURN
* * *
Figure 65. Watchdog Flow Diagram
The second watchdog, refreshed through the WDI2 pin, is useful in applications where safety is a very critical factor and the system must recover from unwanted operations, for example, a processor stuck in a continuous loop where Watchdog 1 is kept refreshed or environmental conditions that may unset or damage the processor port controlling the WDI1 pin. In the event of a Watchdog 2 timeout, the ADP5042 power cycles all the supplied rails to guarantee a clean processor start.
Place the inductor, input capacitor, and output capacitor close to the IC using short tracks. These components carry high switching frequencies, and large tracks act as antennas. Route the output voltage path away from the inductor and SW node to minimize noise and magnetic interference. Maximize the size of ground metal on the component side to help with thermal dissipation. Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes.
Rev. 0 | Page 26 of 32
ADP5042
EVALUATION BOARD SCHEMATICS AND ARTWORK
RFILT 30 AVIN AVIN TP4 L1 1H SW VOUT1 VIN1 C5 4.7F EN1 TP6 VIN2 = 1.7V TO 5.5V C1 1F EN2 VIN2 LDO1 EN_LDO1 WSTAT BUCK EN_BK MODE VOUT2 TP11 TP9 TP10 TP7 nRSTO WDI1 WDI2 C2 1F PGND TP12 TP2 VOUT2 AT 300mA TP1 C6 10F VOUT1 AT 800mA
TP5 VIN1 = 2.3V TO 5.5V
EN3
TP8 VIN3 = 1.7V TO 5.5V VIN3 C3 1F
EN_LDO2 LDO2 VOUT3
SUPERVISOR
AVIN
TP3 VOUT3 AT 300mA C4 1F
08811-068
AGND
Figure 67. Evaluation Board Schematic
SUGGESTED LAYOUT
0.5 1.0 1.5
GPL
2.0
2.5
3.0
3.5
4.0
4.5
5.0
PPL
5.5
6.0
6.5
7.0
3.3V C4 - 1F 6.3V/XR5 0402
mm
0.5
GPL
C3 - 1F 6.3V/XR5 0402
1.0
nRSTO
VOUT3
RFILT 30 0402
VIN3
EN3
PIN 1
1.5
PPL
PPL
PPL
2.0
MODE
NC
MR
2.5
VIN1
3.0
C5 - 4.7F 10V/XR5 0603
GPL
GPL
WDI1
GPL
3.5
L1 - 1H 0603
SW
AGND
WMOD
PGND
GPL
GPL
NC
4.0 EN1
GPL GPL
ADP5042
EN2
4.5
WDI2
5.0
VIN2
GPL
GPL
WSTAT
VOUT1
VOUT2
C6 - 10F 6.3V/XR5 0603
5.5 C1 - 1F 10V/XR5 0402 C2 - 1F 10V/XR5 0402
VIAs LEGEND PPL = POWER PLANE (+4V) GPL = GROUND PLANE TOP LAYER SECOND LAYER
811-069
6.0
1.8V 1.5V
mm
Figure 68. Layout
Rev. 0 | Page 27 of 32
ADP5042
BILL OF MATERIAL
Table 14.
Reference C1, C2, C3, C4 C5 C6 RFILT L1 IC1 Value 1 F, X5R, 6.3 V 4.7 F, X5R, 10 V 10 F, X5R, 6.3 V 30 1 H, 0.09 , 290 mA 1 H, 0.08 , 230 mA 3-regulator micro PMU Part Number LMK105BJ105MV-F LMK107BJ475MA-T JMK107BJ106MA-T BRC1608T1R0M GLFR1608T1R0M-LR ADP5042 Vendor Taiyo Yuden Taiyo Yuden Taiyo Yuden Taiyo Yuden TDK Analog Devices Package 0402 0603 0603 0201/0402 0603 0603 20-Lead LFCSP
APPLICATION DIAGRAM
AVIN RFILT 30 AVIN VIN1 C5 4.7F ON OFF VIN2 = 1.7V TO 5.5V EN1 VIN2 C1 1F ON OFF
6 8
SW VOUT1 PGND
L1 1H C6 10F VOUT1 AT 800mA
VIN1 = 2.3V TO 5.5V
BUCK
7
11 9
EN_BK
FPWM
17 10
MODE
PWM/PSM VOUT2 AT 300mA C2 1F VDD
13
LDO1 (DIGITAL) EN_LDO1
14
VOUT2
EN2 MR
AVIN
16
SUPERVISOR
15
WSTAT nRSTO WDI2 WDI1 VDD
20
PUSH-BUTTON RESET
POFF
RESET WDOG2 WDOG1
5
12 19
ON OFF
EN3
4
17 16
WMOD EN2 NC VOUT3
ON OFF
EN_LDO2 VIN3 = 1.7V TO 5.5V VIN3 C3 1F
3
1 2
LDO2 (ANALOG) AGND
Figure 69. Application Diagram
Rev. 0 | Page 28 of 32
08811-070
C4 1F
VOUT3 AT 300mA
MAIN MICROCONTROLLER
R1
R2
ADP5042 FACTORY PROGRAMMABLE OPTIONS
Table 15. Reset Voltage Threshold Options1
Selection 111 (For VIN = 5 V - 6%) 110 (For VOUT = 3.3 V) 101 (For VOUT = 3.3 V) 100 (For VOUT = 2.8 V) 011 (For VOUT = 2.8 V) 010 (For VOUT = 2.5 V - 6%) 001 (For VOUT = 2.2 V - 6%) 000 (For VOUT = 1.8 V - 6%) Min 3.034 2.886 2.591 2.463 TA = +25C Typ 4.630 3.080 2.930 2.630 2.500 2.350 2.068 1.692 Max 3.126 2.974 2.669 2.538 Min 3.003 2.857 2.564 2.438 TA = -40C to +85C Max 4.700 3.157 3.000 2.696 2.563 2.385 2.099 1.717 Unit V V V V V V V V
Table 16. Reset Timeout Options
Selection 0 1 Min 24 160 Typ 30 200 Max 36 240 Unit ms ms
Table 17. Watchdog 1 Timer Options
Selection 0 1 Min 81.6 1.12 Typ 102 1.6 Max 122.4 1.92 Unit ms sec
Table 18. Watchdog 2 Timer Options
Selection 000 001 010 011 100 101 110 111 Min 6 3.2 6.4 12.8 25.6 51.2 102.4 Typ 7.5 Watchdog 2 disabled 4 8 16 32 64 128 Max 9 4.8 9.6 19.2 38.4 76.8 153.6 Unit sec min min min min min min
Table 19. Power-Off Timing Options
Selection 0 1 Min 140 280 Typ 200 400 Max 280 560 Unit ms ms
Table 20. Reset Sensing Options
Selection 00 01 10 11
1
Monitored Rail VOUT1 pin VOUT2 pin VOUT3 pin AVIN1 pin
When monitoring AVIN, the reset threshold selected, by fuse option or by the external resistor divided, must be higher than the UVLO threshold (2.25 V or 3.6 V).
Rev. 0 | Page 29 of 32
ADP5042 OUTLINE DIMENSIONS
PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.50 BSC 0.30 0.25 0.18
16 15 EXPOSED PAD 20 1
PIN 1 INDICATOR
2.75 2.60 SQ 2.35
5 6
11
TOP VIEW 0.80 0.75 0.70 SEATING PLANE
0.50 0.40 0.30
10
0.25 MIN
BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
Figure 70. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm x 4 mm Body, Very Very Thin Quad (CP-20-8) Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2 ADP5042ACPZ-1-R7 Regulator Settings VOUT1 = 1.8 V VOUT2 = 1.5 V VOUT3 = 3.3 V UVLO = 2.2 V Sequencing: LDO1, LDO2, buck VOUT1 = 1.5 V VOUT2 = 1.8 V VOUT3 = 3.3 V UVLO = 2.2 V Sequencing: LDO1, LDO2, buck ADP5042CP-1-EVALZ ADP5042CP-2-EVALZ
1 2
020509-B
Supervisory Settings WD1 tOUT = 1.6 sec WD2 tOUT = 128 min Reset tOUT = 200 ms POFF = 200 ms VTH Sensing = VOUT3, 2.93 V WD1 tOUT = 1.6 sec WD2 tOUT = 128 min Reset tOUT = 200 ms POFF = 200 ms VTH Sensing = VOUT3, 2.93 V
Temperature Range TJ = -40C to +125C
Package Description 20-Lead Lead Frame Scale Package [LFCSP_WQ]
Package Option CP-20-8
ADP5042ACPZ-2-R7
TJ = -40C to +125C
20-Lead Lead Frame Scale Package [LFCSP_WQ]
CP-20-8
Evaluation Board Evaluation Board
Z = RoHS Compliant Part. Monitoring ambient temperature does not guarantee that the junction temperature (TJ) is within the specified temperature limits.
Rev. 0 | Page 30 of 32
ADP5042 NOTES
Rev. 0 | Page 31 of 32
ADP5042 NOTES
(c)2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08811-0-12/10(0)
Rev. 0 | Page 32 of 32

▲Up To Search▲

Price & Availability of ADP5042

	To Download ADP5042 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .